The present invention relates to a circuit and a method of testing a fail in a memory device. More particularly, the present invention relates to a method of performing a fail test for the whole of a memory device and performing a fail test for each of the bit lines in the memory device.
It is very difficult to manufacture a memory device that is void of defects. Hence, it is impossible to use the memory device in the case that a normal cell as a unit memory element has a fail.
Accordingly, redundancy cell arrays having the same characteristic as a normal cell array are formed in the memory device when the memory device is manufactured.
The above memory device detects whether or not the normal cell array has a fail under a wafer state. Here, in the case that the normal cell array has a fail, the memory device is discarded or a redundancy cell is substituted for a normal cell having a fail.
FIG. 1 is a plan view illustrating a common circuit for testing a fail.
FIG. 1 shows a part of the memory device having a circuit for measuring a current passing through a bit line by using a current mirror, and discriminating whether or not a fail has occurred in the memory device through the measured current.
In FIG. 1, the memory device includes a memory cell array 110 having at least one bit line connected to a plurality of memory cells for storing data, a page buffer section 120 having a plurality of page buffers PBq to PBn for programming or reading data of the memory cell connected to a pair of bit lines included in the memory cell array 110, a current comparing section 130 having comparing circuits iPBq to iPBn for comparing a reference current with a current passing through the page buffers PBq to PBn and outputting the comparison result, a current measuring section 140 for measuring a total current i1 passing through the current comparing section 130 by using the current mirror, and an adjusting section 150 for adjusting a level of a current passing through the current measuring section 140.
A total current passing through the page buffer section 120 and outputted to the current comparing section 130 is the current i1 passing through a third node 3. In addition, the current i1 passing through the third node 3 is identical to a current i2 passing through a fourth node 4 because the current measuring section 140 is made up of the current mirror.
The current mirror section 140 includes a first P-MOS transistor P1, a second P-MOS transistor P2, a first inverter IN1 and a second inverter IN2. Here, the P-MOS transistors P1 and P2 form the current mirror, and so the current i1 is identical to the current i2 which passes through the fourth node 4.
The fourth node 4 is connected to the adjusting section 150.
The adjusting section 150 includes a plurality of current paths operated by control circuits B1 to Bn.
The control circuits B1 to Bn may have transistors for controlling each of current paths. Accordingly, the level of the current passing through the fourth node 4 may be adjusted by the current i2 and the adjusting section 150.
Therefore, a program of a memory cell connected to each of the page buffers PBq to PBn is determined in accordance with an inputted data, and so the current is changed depending on the program. Additionally, the control circuits B1 to Bn of the adjusting section 150 are controlled by using the changed current, and thus the level of the current of the fourth node 4 is adjusted. Further, the first inverter IN1 and the second inverter IN2 change a value of the fourth node 4 as an analog value into a digital value in accordance with the level of the current of the fourth node 4, and then output the digital value.
Hereinafter, a process of operating the circuit for testing a fail of a bit line will be described in detail.
FIG. 2 is a flow chart illustrating a method of testing a fail of a bit line by using the circuit in FIG. 1.
Referring to FIG. 2, in the case that a program command, an address and data to be programmed are inputted to the memory device in steps of S201 to S205, a program pulse is provided in step of S207. As a result, data in the memory cell related to the address are programmed. In this case, the bit lines connected to the programmed memory cell are connected to the page buffers PBq to PBn of the page buffer section 120.
In steps of S209 to S211, when the current i2 is changed in accordance with the current i1 passing through every page buffer PBq to PBn, the fourth node 4 is connected in sequence to the control circuits B1 to Bn, and then the currents passing through the page buffers PBq to PBn are tested, respectively. Subsequently, the number of the bit line to which a fail has occurred is scanned. In the case that the test is passed, it is discriminated whether or not a fail has occurred in the bit line by reading several times the control circuits B1 to Bn.
In steps of S209 to S215, the control circuits B1 to Bn operate in sequence to measure the currents passing through every page buffer PBq to PBn so as to verify whether or not a fail has occurred in the bit lines. Then, the bit lines to which the fail has occurred are verified by scanning.
The process of verifying the fail of the bit line by measuring the current is done by reading several times the control circuits B1 to Bn. Hence, power consumption is great and much time is required for the verification.
In addition, the fail of the bit line is tested by measuring the currents passing through each of the page buffers PBq to PBn. However, a method of performing a fail test for the whole of the memory device does not exist in a conventional art.
Accordingly, a fail test for the whole of the memory device is performed by only testing the fail of every bit line and then scanning the number of the bit lines to which a fail has occurred. Further, the test method would always consume a constant current because the reference voltage is used. In other words, power is always consumed.